AAT3603 datasheet(32/35 Pages) ANALOGICTECH

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AAT3603178

Total Power Solution for Portable Applications

PRODUCT DATASHEET

3603.2008.06.1.0

www .analogictech.com

LDO11

LDO10

LDO1 Output Voltage

3.00V (default)

2.90V

2.85V

2.80V

LDO21

LDO20

LDO2 Output Voltage

3.00V (default)

2.90V

2.85V

2.80V

LDO31

LDO30

LDO3 Output Voltage

3.00V (default)

2.90V

2.85V

2.80V

LDO41

LDO40

LDO4 Output Voltage

3.00V (default)

2.90V

2.85V

2.80V

LDO51

LDO50

LDO5 Output Voltage

3.00V (default)

2.90V

2.85V

2.80V

Table 7: LDO Bit Setting for

LDO Output Voltage Level.

Layout Guidance

Figure 10 is the schematic for the evaluation board. The

evaluation board has extra components for easy evalua-

tion; the actual BOM need for a system is shown in Table

9. When laying out the PC board, the following layout

guideline should be followed to ensure proper operation

of the AAT3603:

1. The exposed pad EP must be reliably soldered to

PGND/AGND and multilayer GND. The exposed ther-

mal pad should be connected to board ground plane

and pins 2 and 16. The ground plane should include

a large exposed copper pad under the package with

VIAs to all board layers for thermal dissipation.

2. The power traces, including GND traces, the LX

traces and the VIN trace should be kept short, direct

and wide to allow large current flow. The L1 connec-

tion to the LX pins should be as short as possible.

Use several via pads when routing between layers.

3. The input capacitors (C1 and C2) should be con-

nected as close as possible to CHGIN (Pin 28) and

PGND (Pin 2) to get good power filtering.

4. Keep the switching node LX away from the sensitive

OUTBUCK feedback node.

5. The feedback trace for the OUTBUCK pin should be

separate from any power trace and connected as

closely as possible to the load point. Sensing along a

high current load trace will degrade DC load regula-

tion.

6. The output capacitor C4 and L1 should be connected

as close as possible and there should not be any

signal lines under the inductor.

7. The resistance of the trace from the load return to

the PGND (Pin 2) should be kept to a minimum. This

will help to minimize any error in DC regulation due

to differences in the potential of the internal signal

ground and the power ground.

Quantity

Value

Designator

Footprint

Description

510μF

C1, C2, C3, C14, C15

0603

Capacitor, Ceramic, X5R, 6.3V, ±20%

222μF

0805

Capacitor, Ceramic, 20%, 6.3V, X5R

4.7μF

C4, C5, C6, C7, C8

0603

Capacitor, Ceramic, 20%, 6.3V, X5R

0.1μF

C10, C11, C12

0402

Capacitor, Ceramic, 16V, 10%, X5R

0.01μF

C13

0402

Capacitor, Ceramic, 16V, 10%, X7R

3.3μH

CDRH2D

Inductor, Sumida CDRH2D11NP-3R3NC

100K

R5, R8, R20, R21, R22, R23, R25, R26, R27

0402

Resistor, 5%

10K

R17, R19, R24, R29, R31, R32, R33, R37

0402

Resistor, 5%

1.24K

R18

0402

Resistor, 1%

Table 8: Minimum AAT3603 Bill of Materials.

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