LFSC datasheet(70/237 Pages) LATTICE

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3-26

DC and Switching Characteristics

Lattice Semiconductor

LatticeSC/M Family Data Sheet

sysCLOCK DLL Timing

Over Recommended Operating Conditions

Parameter

Description

Conditions

Min.

Typ.

Max.

Units

fIN

Input Clock Frequency (CLKI, CLKFB)

100

—

700

MHz

fOUTOP

Output Clock Frequency (CLKOP)

100

—

700

MHz

fOUTOS

Output Clock Frequency (CLKOS)

—

700

MHz

AC Characteristics

tDUTY

Output Clock Duty Cycle

Output Clock Duty Cycle (at 50%

levels, 50% duty cycle input clock,

duty cycle correction turned off,

time reference delay mode)

38—62

tDUTYRD

Output Clock Duty Cycle

Output Clock Duty Cycle (at 50%

levels, arbitrary duty cycle input

clock, duty cycle correction turned

on, time reference delay mode)

45—55

tDUTYCIR

Output Clock Duty Cycle

Output Clock Duty Cycle (at 50%

levels, arbitrary duty cycle input

clock, duty cycle correction turned

on, clock injection removal mode)

40—60

tOPJIT

Output Clock Period Jitter

—

200

tCPJIT

Output Clock Cycle-to-Cycle Jitter

—

200

tSKEW

Output Clock to Clock Skew (Between

Two Outputs with the Same Phase

Setting)

—

100

tLOCK

DLL Lock-in Time

—

18500

cycles

tIDUTY

Input Clock Duty Cycle

Applies to all operating conditions

—

tIPJIT

Input Clock Period Jitter

—

+/- 250

tHI

Input Clock High Time

At 80% level

500

—

tLO

Input Clock Low Time

At 20% level

500

—

tRSWD

Reset Signal Pulse Width

—

tFDEL

Timeshift Delay Step Size

tDLL

Delay Through the DLL when No Delay

Taps are Chosen but Not in Bypass

Mode.

—

760

—

1. Values are measured with FPGA logic active, no additional I/Os toggling and REFCLK total jitter = 30 ps.

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