LFSC datasheet(12/237 Pages) LATTICE

12 / 237 page

2-8

Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

Figure 2-6. Per Quadrant Clock Selection

Secondary Clocks

In addition to the primary clock network and edge clocks the LatticeSC devices also contain a secondary clock net-

work. Built of X6 style routing elements this secondary clock network is ideal for routing slower speed clock and

control signals throughout the device preserving high-speed clock networks for the most timing critical signals.

Edge Clocks

LatticeSC devices have a number of high-speed edge clocks that are intended for use with the PIOs in the imple-

mentation of high-speed interfaces. There are eight edge clocks per bank for the top and bottom of the device. The

left and right sides have eight edge clocks per side for both banks located on that side. Figure 2-7 shows the

arrangement of edge clocks.

Edge clock resources can be driven from a variety of sources. Edge clock resources can be driven from:

• Edge clock PIOs in the same bank

• Primary clock PIOs in the same bank

• Routing

• Adjacent PLLs and DLLs

• ELSR output from the clock divider

12 Primary Clock per Quadrants

12 feedlines per quadrants times 4 + 12 feedlines from upper and lower half

12 Primary Clocks

60 Primary Clock Sources

GND

From Local

Routing

From Local

Routing

From Local

Routing

Note: GND is available to switch off the network.

LFSC Datasheet(PDF) 12 Page - Lattice Semiconductor