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LFSC Datasheet(PDF) 72 Page - Lattice Semiconductor |
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LFSC Datasheet(HTML) 72 Page - Lattice Semiconductor |
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72 / 237 page  3-28 DC and Switching Characteristics Lattice Semiconductor LatticeSC/M Family Data Sheet sysCONFIG MPI Port sysCONFIG Asynchronous Peripheral Configuration Mode tWRAP WRN, CS0N and CS1 Pulse Width 5 - ns tSAP D[7:0] Setup Time 1.5 - ns tRDYAP RDY Delay — 8 ns tBAP RDY Low 1 8 CCLK periods tWR2AP Earliest WRN After RDY Goes High 0 — ns tDENAP RDN to D[7:0] Enable/Disable — 7.5 ns tDAP CCLK to DOUT — 7.5 ns sysCONFIG Slave Serial Configuration Mode tSSS DIN Setup Time 5.2 — ns tHSS DIN Hold Time 0 — ns tCHSS CCLK High Time 3.75 — ns tCLSS CCLK Low Time 3.75 — ns fCSS CCLK Frequency — 150 MHz tDSS CCLK to DOUT — 7.5 ns sysCONFIG Slave Parallel Configuration Mode tS1SP CS0N, CS1, WRN Setup Time 5.2 — ns tH1SP CS0N, CS1, WRN Hold Time 0 — ns tS2SP D[7:0] Setup Time 5.2 — ns tH2SP D[7:0] Hold Time 0 — ns tCHSP CCLK High Time 3.75 — ns tCL CCLK Low Time 3.75 — ns fCSP CCLK Frequency — 150 MHz Parameter Description -7 -6 -5 Units Min. Max. Min. Max. Min. Max. tMPICTRL_SET MPI Control (MPCSTRBN, MPCWRN, MPCCLK, etc.) to MPCCLK Setup Time 4.9 — 5.2 — 5.5 — ns tMPIADR_SET MPI Address to MPCCLK Setup Time 3.9 — 4.2 — 4.5 — ns tMPIDAT_SET MPI Write Data to MPCCLK Setup Time 4.9 — 5.2 — 5.5 — ns tMPIDPAR_SET MPI Write Parity Data to MPCCLK Setup Time 3.9 — 4.2 — 4.5 — ns tMPI_HLD All Hold Times 0—0—0— ns tMPICTRL_DEL MPCCLK to MPI Control (MPCTA, MPC- TEA, MPCRETRY) — 5.6 — 6.7 — 8.7 ns tMPIDAT_DEL MPCCLK to MPI Data — 5.6 — 6.7 — 8.7 ns tMPIDPAR_DEL MPCCLK to MPI Parity Data — 4.9 — 5.7 — 7.7 ns fMPI_CLK_FRQ MPCCLK Frequency — 100 — 83 — 66 MHz LatticeSC/M sysCONFIG Port Timing (Continued) Over Recommended Operating Conditions Parameter Description Min. Max. Units |
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