33742 datasheet(30/70 Pages) FREESCALE

30 / 70 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33742

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

mode over-current situation or from forced wake-up, no bits

are set. After the INT pulse, the 33742 accepts SPI command

after a time delay (tS-1STSPI).

WATCHDOG SOFTWARE IN STOP MODE

If the SBC watchdog is enabled, the application must

provide a “system ok” response before the end of the 33742

watchdog time. Typically an MCU initiates the wake-up of the

33742 through the SPI wake-up (CS activation). The SBC will

awaken and jump into the Normal Request mode. The MCU

has to configure the 33742 to go to either Normal or Standby

mode. The MCU can then decide to return to the Stop mode.

If no MCU wake-up occurs within the watchdog time

period, the SBC activates the RST pin and jumps into the

Normal Request mode. The MCU can then be re-initialized.

STOP MODE ENTER COMMAND

Stop mode is entered at the end of the SPI message at the

rising edge of the CS. (Refer to the t CS-STOP data in the

Dynamic Electrical Characteristics table on page 17.) Once

Stop mode is entered, the SBC can wake up from a VDD

regulator over-current detection state. In order to allow time

for the MCU to complete the last CPU instruction and enter

its low power mode, a deglitcher time of 40

μs typical is

implemented.

Figure 11, page 30, depicts the operation of entering the

Stop mode.

Figure 11. Entering the Stop Mode

WATCHDOG SOFTWARE (RST AND WDOG)

(SELECTABLE WATCHDOG WINDOW OR

WATCHDOG TIME-OUT)

A watchdog is used in the SBC Normal and Standby

modes for monitoring the MCU operation. The watchdog

timer may be implemented as either a watchdog window or

watchdog timeout, selectable by SPI (TIM1 sub register, bit

WDW). Default operation is a watchdog window.

The watchdog period can be set from 10ms to 350ms

(TIM1 sub register, bits WDT0 and WDT1). When a watchdog

window is selected, the closed window is the first part of the

selected period, and the open window is the second part of

the period. (Refer to Timing Register (TIM1/2) beginning on

page 52.)

The watchdog can only be cleared within the open window

time period. Any attempt to clear watchdog in the closed

window will generate a reset. The watchdog is cleared

addressing the TIM1 sub register using the SPI

RST PIN DESCRIPTION

A 33742 output is available to perform a reset of the MCU.

Reset can happen from:

•VDD Falling Out of Range—If VDD falls below the reset

threshold (VRSTTH), the RST pin is pulled LOW until

VDD returns to the normal voltage.

• Power-ON Reset—At 33742 power-on or wake-up from

Sleep mode, the RST pin is maintained LOW until VDD

is within its operation range.

• Watchdog Timeout—If watchdog is not cleared, the

33742 will pull the RST pin LOW for the duration of the

reset time (tRSTDUR).

RST AND WDOG OPERATION

Table 8 describes watchdog and reset output modes of

operation. RST is activated in the event VDD fall or watchdog

is not triggered. WDOG output is active LOW as soon as RST

goes LOW and stays LOW as long as the watchdog is not

properly reset via SPI. The WDOG output pin is designed as

a push-pull structure that can drive off chip components

signaling, for instance, errant MCU operation.

Figure 12 illustrates the device behavior in the event the

TIM1 register in not properly accessed. In this case, a

software reset occurs and the WDOG pin is set LOW until the

TIM1 register is properly accessed.

SPI CS

SPI Stop/Sleep

Command

33742 in Normal

or Standby mode

33742 in Stop mode.

No IDD over IDD-DGLT

33742 in Stop mode.

IDD over IDD-DGLT

tCS-STOP

tIDD-DGLT

33742 Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

33742 Datasheet(HTML) 30 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL