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HD404849FS Datasheet(PDF) 14 Page - Renesas Technology Corp |
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HD404849FS Datasheet(HTML) 14 Page - Renesas Technology Corp |
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14 / 127 page  HD404849 Series 12 bit3 bit2 bit1 bit0 Interrupt control bits area $000 $003 SMRA $005 SRL $006 SRU $007 TMB1 $009 TRBL/TWBL $00A TRBU/TWBU $00B MIS $00C TMC1 $00D TRCL/TWCL $00E TRCU/TWCU $00F TMD1 $010 TRDL/TWDL $011 TRDU/TWDU $012 TMB2 $013 TMC2 $014 TMD2 $015 AMR $016 ADRL $017 ADRU $018 LCR $01B LMR $01C LOR3 $01F $020 PMRB $024 PMRC $025 ESR1 $026 ESR2 $027 SMRB $028 SSR $029 DCD0 $02C DCD1 $02D DCD2 $02E DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 DCR6 $036 DCR7 $037 V $03F PMRA $004 TMA $008 $023 R22/SI R23/SO R21/ SCK Serial transmit clock speed selection 1 Timer A/time base Clock source selection (timer A) Auto reload on/off Clock source selection (timer B) Timer B register (upper digit) Pull-up MOS control PMOS SO control Timer C output mode selection Analog channel selection A/D conversion period *1 *2 LCD power switch LCD display on/off R7/SEG17–20 R6/SEG13–16 R02/INT3 R01/INT2 D10/ STOPC R20/EVND R13/ EVNB INT2 detection edge selection *3 *4 32-kHz oscillation stop *5 *6 Port D3 DCR Port D2 DCR Port D1 DCR Port D0 DCR Port D7 DCR Port D6 DCR Port D5 DCR Port D4 DCR Port D8 DCR Port R03 DCR Port R02 DCR Port R01 DCR Port R00 DCR Port R13 DCR Port R12 DCR Port R11 DCR Port R10 DCR Port R23 DCR Port R22 DCR Port R21 DCR Port R20 DCR Port R33 DCR Port R32 DCR Port R31 DCR Port R30 DCR Port R63 DCR Port R62 DCR Port R61 DCR Port R60 DCR Port R73 DCR Port R72 DCR Port R71 DCR Port R70 DCR Bank selection Auto reload on/off Input capture selection Serial data register (lower digit) Serial data register (upper digit) Timer B register (lower digit) Interrupt frame period selection Clock source selection (timer C) Timer C register (lower digit) Timer C register (upper digit) Clock source selection (timer D) Timer D register (lower digit) Timer D register (upper digit) Timer B output mode selection Timer D output mode selection A/D data register (lower digit) A/D data register (upper digit) LCD input clock source selection LCD duty cycle selection Register flag area INT3 detection edge selection EVND detection edge selection D11/ INT0 R00 / INT1 4. 5. 6. Transmit clock source selection 32-kHz oscillation division ratio System oscillation frequency selection 1. 2. 3. LCD display division resistor switch Display on/off in watch mode SO output level control in idle states Notes: Auto reload on/off Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Figure 5 Special Function Register Area |
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