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7480 Datasheet(PDF) 48 Page - Renesas Technology Corp |
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7480 Datasheet(HTML) 48 Page - Renesas Technology Corp |
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48 / 98 page ![]() 47 MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. EPROM MODE The built-in programmable ROM has the EPROM mode in addition _____ to its normal operation modes. When the RESET level becomes “L”, the chip automatically enters the EPROM mode. Table 6 shows a list of correspondence between pins and Figure 50 to Fig- ure 52 show pin connection diagrams. In this status, each of ports P0, P11 to P17, P20 to P23, P3, P40, P41 and VREF are used for the PROM (equivalent to M5M27C256K). In this mode, the built-in PROM can be written to or read from using these pins in the same way as with the M5M27C256K. The clock should be connected to XIN and XOUT pins. Table 6. Correspondence between pins in EPROM mode M37480E8, M37481E8 VCC P33 VSS Ports P11 – P17, P20 – P23, P30, P31, P40, P41 Port P0 VREF P32 VCC VPP VSS Address input Data I/O __ CE __ OE M5M27C256K VCC VPP VSS A0 – A14 D0 – D7 __ CE __ OE Fig. 50 Pin connection in EPROM mode (1) Outline 42P4B 42S1B-A (M37481E8SS) A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSS CE D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 VPP A12 A11 VCC OE VSS : PROM pin (equivalent to M5M27C256K) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 28 29 30 31 32 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1 P30/INT0 RESET VCC 17 26 25 24 23 22 18 19 20 21 27 33 35 36 37 38 39 40 41 42 34 P53 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P52 P51 P50 P43 P42 |
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