SH7261 datasheet(104/1348 Pages) RENESAS

104 / 1348 page

Section 3 Floating-Point Unit (FPU)

Rev. 2.00 Sep. 07, 2007 Page 72 of 1312

REJ09B0320-0200

3.3.2

Floating-Point Status/Control Register (FPSCR)

FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and

selects the rounding mode.







Bit:

000000000

0100

0000000001

Initial value:

RRRRRRRRR

R/W

Enable

Flag

Cause

RM1

QIS

RM0

Cause

R/W

R/W:

Bit:

Initial value:

R/W:

9876543210

R/W

Bit

Bit Name

Initial

Value

R/W

Description

31 to 23

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

QIS

R/W

Nonnunerical Processing Mode

0: Processes qNaN or

±∞ as such

1: Treats qNaN or

±∞ as the same as sNaN (valid only

when the V bit in FPSCR enable is set to 1)

—

Reserved

This bit is always read as 0. The write value should

always be 0.

R/W

Transfer Size Mode

0: Data size of FMOV instruction is 32-bits

1: Data size of FMOV instruction is a 32-bit register

pair (64 bits)

R/W

Precision Mode

0: Floating-point instructions are executed as

single-precision operations

1: Floating-point instructions are executed as

double-precision operations (graphics support

instructions are undefined)

Denormalization Mode (Always fixed to 1 in SH2A-

FPU)

1: Denormalized number is treated as zero

SH7261 Datasheet(PDF) 104 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 104 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL