SH7261 datasheet(120/1348 Pages) RENESAS

120 / 1348 page

Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 Sep. 07, 2007 Page 88 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

CKOEN

R/W

Clock Output Enable

Specifies whether a clock is output from the CKIO

pin, or whether the CKIO pin is placed in the level-

fixed state during software standby mode or

cancellation of software standby mode.

If this bit is cleared to 0, the CKIO pin is fixed at low

during software standby mode or cancellation of

software standby mode. Therefore, the malfunction of

an external circuit because of an unstable CKIO

clock during cancellation of software standby mode

can be prevented. In clock operating mode 3, the

CKIO pin functions as an input regardless of this bit

value.

0: The CKIO pin is fixed to the low level during

software standby mode or cancellation of software

standby mode.

1: Clock is output from CKIO pin (low level in

software standby mode).



Reserved

This bit is always read as 0. The write value should

always be 0.

10 to 8

STC[2:0]

000

R/W

Frequency Multiplication Ratio of PLL Circuit 1

000:

× 1 time

001:

× 2 times

010:

× 3 times

011:

× 4 times

100:

× 6 times

101:

× 8 times



Reserved

This bit is always read as 0. The write value should

always be 0.

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