SH7261 datasheet(124/1348 Pages) RENESAS

124 / 1348 page

Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 Sep. 07, 2007 Page 92 of 1312

REJ09B0320-0200

4.5.2

Changing the Division Ratio

Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is

not.

1. In the initial state, IFC[2:0]

= B'000 and PFC[2:0] = B'011.

2. Set the desired value in the IFC[2:0] and PFC[2:0] bits. The values that can be set are limited

by the clock operating mode and the multiplication rate of PLL circuit 1. Note that if the wrong

value is set, this LSI will malfunction.

3. After the register bits (IFC[2:0] and PFC[2:0]) have been set, the clock is supplied of the new

division ratio.

Note:

When executing the SLEEP instruction after the frequency has been changed, be sure to

read the frequency control register (FRQCR) three times before executing the SLEEP

instruction.

4.6

Notes on Board Design

4.6.1

Note on Inputting External Clock

Figure 4.2 is an example of connecting the external clock input. When putting the XTAL pin in

open state, make sure the parasitic capacitance is less than or equal to 10 pF. To stably input the

external clock with enough PLL stabilizing time at power on or releasing the standby, wait longer

than the oscillation stabilizing time.

EXTAL

XTAL

Example of connection with XTAL pin open

Open state

External clock input

Figure 4.2 Example of Connecting External Clock

For details on input conditions of the external clock, see section 31.3.1, Clock Timing.

SH7261 Datasheet(PDF) 124 Page - Renesas Technology Corp