SH7261 datasheet(121/1348 Pages) RENESAS

121 / 1348 page

Section 4 Clock Pulse Generator (CPG)

Rev. 2.00 Sep. 07, 2007 Page 89 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

6 to 4

IFC[2:0]

000

R/W

Internal Clock Frequency Division Ratio

These bits specify the frequency division ratio of the

internal clock with respect to the output frequency of

PLL circuit 1.

000:

× 1 time

001:

× 1/2 time

010:

× 1/3 time

011:

× 1/4 time

100:

× 1/6 time

101:

× 1/8 time

RNGS

R/W

Output Range Select for PLL Circuit 1

When the multiplication ratio for the PLL circuit 1 is

specified to

× 3, set this bit according to the output

frequency of the PLL circuit 1.

0: Low frequency mode

(Output frequency of the PLL circuit 1 is equal to

or smaller than 120 MHz.)

1: High frequency mode

(Multiplication ratio for the PLL circuit 1 is specified

× 3 and its output frequency exceeds 120 MHz.)

2 to 0

PFC[2:0]

011

R/W

Peripheral Clock Frequency Division Ratio

These bits specify the frequency division ratio of the

peripheral clock with respect to the output frequency

of PLL circuit 1.

000:

× 1 time

001:

× 1/2 time

010:

× 1/3 time

011:

× 1/4 time

100:

× 1/6 time

101:

× 1/8 time

110:

× 1/12 time

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