HD6417618 datasheet(513/646 Pages) RENESAS

513 / 646 page

Section 18 User Break Controller (UBC)

Rev. 6.00 Jun. 12, 2007 Page 481 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

PCBB

R/W

PC Break Select B

Selects the break timing of the instruction fetch cycle for

channel B as before or after instruction execution.

0: PC break of channel B is set before instruction

execution

1: PC break of channel B is set after instruction

execution

5, 4

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SEQ

R/W

Sequence Condition Select

Selects two conditions of channels A and B as

independent or sequential conditions.

0: Channels A and B are compared under independent

conditions

1: Channels A and B are compared under sequential

conditions (channel A, then channel B)

2, 1

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

ETBE

R/W

Number of Execution Times Break Enable

Enables the execution-times break condition only on

channel B. If this bit is 1 (break enable), a user break is

issued when the number of break conditions matches

with the number of execution times that is specified by

BETR.

0: The execution-times break condition is disabled on

channel B

1: The execution-times break condition is enabled on

channel B

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