HD6417618 datasheet(510/646 Pages) RENESAS

510 / 646 page

Section 18 User Break Controller (UBC)

Rev. 6.00 Jun. 12, 2007 Page 478 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

CDB1

CDB0

R/W

L Bus Cycle/I Bus Cycle Select B

Select the L bus cycle or I bus cycle as the bus cycle of the

channel B break condition.

00: Condition comparison is not performed

01: The break condition is the L bus cycle

10: The break condition is the I bus cycle

11: The break condition is the L bus cycle

IDB1

IDB0

R/W

Instruction Fetch/Data Access Select B

Select the instruction fetch cycle or data access cycle as

the bus cycle of the channel B break condition.

00: Condition comparison is not performed

01: The break condition is the instruction fetch cycle

10: The break condition is the data access cycle

11: The break condition is the instruction fetch cycle or

data access cycle

RWB1

RWB0

R/W

Read/Write Select B

Select the read cycle or write cycle as the bus cycle of the

channel B break condition.

00: Condition comparison is not performed

01: The break condition is the read cycle

10: The break condition is the write cycle

11: The break condition is the read cycle or write cycle

SZB1

SZB0

R/W

Operand Size Select B

Select the operand size of the bus cycle for the channel B

break condition.

00: The break condition does not include operand size

01: The break condition is byte access

10: The break condition is word access

11: The break condition is longword access

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