HD6417618 datasheet(517/646 Pages) RENESAS

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Section 18 User Break Controller (UBC)

Rev. 6.00 Jun. 12, 2007 Page 485 of 610

REJ09B0131-0600

18.3.2

Break on Instruction Fetch Cycle

1. When L bus/instruction fetch/read/word or longword is set in the break bus cycle register

(BBRA/BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it

breaks before or after the execution of the instruction can then be selected with the

PCBA/PCBB bit of the break control register (BRCR) for the appropriate channel. If an

instruction fetch cycle is set as a break condition, clear LSB in the break address register

(BARA/BARB) to 0. A break cannot be generated as long as this bit is set to 1.

2. If the condition is matched while a break before execution is selected, a break is generated

when it is confirmed that the instruction has been fetched and it will be executed. This means

this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch

or during an interrupt transition, but not to be executed). When this kind of break is set in the

delay slot of a delayed branch instruction, the break is generated immediately before the

execution of the instruction that first accepts the break. Meanwhile, a break before the

execution of the instruction in a delay slot and a break after the execution of the SLEEP

instruction are also prohibited.

3. When a break after execution is selected, the instruction that matches the break condition is

executed and then the break is generated prior to the execution of the next instruction. As with

a break before execution, this cannot be used with overrun fetch instructions. When this kind

of break is set for a delayed branch instruction, a break is not generated until the first

instruction at which breaks are accepted.

4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is

ignored. There is thus no need to set break data for the break of the instruction fetch cycle.

18.3.3

Break on Data Access Cycle

• The bus cycles in which L bus data access breaks occur are from instructions.

• The relationship between the data access cycle address and the comparison condition for each

operand size is listed in table 18.1.

Table 18.1

Data Access Cycle Addresses and Operand Size Comparison Conditions

Access Size

Address Compared

Longword

Compares break address register bits 31 to 2 to address bus bits 31 to 2

Word

Compares break address register bits 31 to 1 to address bus bits 31 to 1

Byte

Compares break address register bits 31 to 0 to address bus bits 31 to 0

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