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HD6417618 Datasheet(PDF) 226 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 226 Page - Renesas Technology Corp |
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226 / 646 page  Section 8 Clock Pulse Generator (CPG) Rev. 6.00 Jun. 12, 2007 Page 194 of 610 REJ09B0131-0600 A block diagram of the CPG is shown in figure 8.1. CKIO PLL circuit 1 ( ×1, ×2) PLL circuit 2 ( ×2, ×4) ×1 ×1/2 ×1/4 ×1 ×1/2 ×1/4 Oscillator unit Internal clock (I φ) Internal bus Bus interface [Legend] FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby control register 2 STBCR3: Standby control register 3 STBCR4: Standby control register 4 MCLKCR: PHY-LSI clock frequency control register Peripheral clock (P φ) Bus clock (B φ = CKIO) EXTAL FRQCR STBCR STBCR2 STBCR3 STBCR4 CPG control unit PHY clock (M φ) Clock frequency control circuit Standby control circuit Divider 1 MD2 MD1 MD0 XTAL Crystal oscillator Divider 2 MCLKCR CK-PHY Figure 8.1 Block Diagram of CPG |
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