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HD6432147SW Datasheet(PDF) 393 Page - Renesas Technology Corp |
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HD6432147SW Datasheet(HTML) 393 Page - Renesas Technology Corp |
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393 / 1177 page  Section 12 8-Bit Timers Rev. 4.00 Sep 27, 2006 page 349 of 1130 REJ09B0327-0400 Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. Note that an OVI interrupt is not requested by TMRX, regardless of the OVIE value. Bit 5 OVIE Description 0 OVF interrupt request (OVI) is disabled (Initial value) 1 OVF interrupt request (OVI) is enabled Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select the method by which the timer counter is cleared: by compare-match A or B, or by an external reset input. Bit 4 Bit 3 CCLR1 CCLR0 Description 0 0 Clearing is disabled (Initial value) 1 Cleared on compare-match A 1 0 Cleared on compare-match B 1 Cleared on rising edge of external reset input |
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