HD6432147SW datasheet(394/1177 Pages) RENESAS

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Section 12 8-Bit Timers

Rev. 4.00 Sep 27, 2006 page 350 of 1130

REJ09B0327-0400

Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to

TCNT is an internal or external clock.

The input clock can be selected from either six or three clocks, all divided from the system clock

(

φ). The falling edge of the selected internal clock triggers the count.

When use of an external clock is selected, three types of count can be selected: at the rising edge,

the falling edge, and both rising and falling edges.

Some functions differ between channel 0 and channel 1, because of the cascading function.

TCR

STCR

Bit 2 Bit 1 Bit 0

Bit 1

Bit 0

Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description

—

Clock input disabled

(Initial value)

001

—

φ/8 internal clock source, counted on the falling edge

001

—

φ/2 internal clock source, counted on the falling edge

010

—

φ/64 internal clock source, counted on the falling

edge

010

—

φ/32 internal clock source, counted on the falling

edge

011

—

φ/1024 internal clock source, counted on the falling

edge

011

—

φ/256 internal clock source, counted on the falling

edge

—

Counted on TCNT1 overflow signal*

—

Clock input disabled

(Initial value)

001

—

φ/8 internal clock source, counted on the falling edge

001

—

φ/2 internal clock source, counted on the falling edge

010

—

φ/64 internal clock source, counted on the falling

edge

010

—

φ/128 internal clock source, counted on the falling

edge

011

—

φ/1024 internal clock source, counted on the falling

edge

011

—

φ/2048 internal clock source, counted on the falling

edge

—

Counted on TCNT0 compare-match A*

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