SH7014 datasheet(10/754 Pages) RENESAS

10 / 754 page

Rev.5.00 Sep. 27, 2007 Page x of xxxiv

REJ09B0398-0500

Item

Page

Revision (See Manual for Details)

9.3.6 DMA Transfer

Ending Conditions

Conditions for Ending All

Channels

Simultaneously:

187

Description amended

When the processing of a one unit transfer is complete. In a

dual address mode direct address transfer, even if an address

error occurs or the NMI flag is set during read processing, the

transfer will not be halted until after completion of the following

write processing. In such a case, SAR, DAR, and DMATCR

values are updated.

9.4.2 Example of DMA

Transfer between

External RAM and

External Device with

DACK

189

Description amended

In this example, an external request, single address mode

transfer with external memory as the transfer source and an

external device with DACK as the transfer destination is

executed using DMAC channel 1.

10.1.1 Features

191

Description amended

⎯ PWM mode: PWM output can be provided with any duty

cycle. When combined with the counter synchronizing

function, up to seven-phase PWM output is enabled

(with channels 0 to 2 set to PWM mode 2 and channel 0

synchronized with the TGR0A register (channels 0 to 2

phase output: 3, 2, 2)).

10.1.4 Register

Configuration

Table 10.3 Register

Configuration

198

Notes amended

Notes: Do not access empty addresses.

1. 16-bit registers (TCNT, TGR) cannot be read or

written in 8-bit units.

2. Write 0 to clear flags.

10.2.4 Timer Interrupt

Enable Register (TIER)

Bit 5—Underflow

Interrupt Enable

(TCIEU)

215

Description amended

This bit is reserved for channel 0. It always reads as 0. The

write value should always be 0.

Bit 3—TGR Interrupt

Enable D (TGIED):

216

Description amended

This bit is reserved for channels 1 and 2. It always reads as 0.

The write value should always be 0.

Bit 2—TGR Interrupt

Enable C (TGIEC):

Description amended

This bit is reserved for channels 1 and 2. It always reads as 0.

The write value should always be 0.

10.2.5 Timer Status

217

Description amended

The timer status register (TSR) is an 8-bit register that indicates

the status of each channel. The MTU has three TSR registers,

one each for channel. TSR is initialized to H'C0 by a power-on

reset or by standby mode.

SH7014 Datasheet(PDF) 10 Page - Renesas Technology Corp

SH7014 Datasheet(HTML) 10 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL