SH7014 datasheet(19/754 Pages) RENESAS

19 / 754 page

Rev.5.00 Sep. 27, 2007 Page xix of xxxiv

REJ09B0398-0500

Item

Page

Revision (See Manual for Details)

18.7.3 Erase Mode

517

Description added

When erasing flash memory, the erase/erase-verify flowchart

shown in figure 18.14 should be followed.

To perform data or program erasure, set the 1 bit flash memory

area to be erased in erase block register 1 (EBR1) at least 10

µs after setting the SWE bit to 1 in flash memory control

18.8.2 Software

Protection

525

Description amended

Software protection can be implemented by setting the SWE bit

in FLMCR1, erase block register 1 (EBR1) and the RAMS bit in

the RAM emulation register (RAMER).

18.11.4 Auto-Program

Mode

538

Description amended

3. The lower 8 bits of the transfer address must be H'00, H'80.

If a value other than an effective address is input,

processing will switch to a memory write operation but a

write error will be flagged.

4. Memory address transfer is performed in the second cycle

(figure 18.24). Do not perform transfer after the third cycle.

18.11.6 Status Read

Mode

Table 18.19 Status

Read Mode Return

Commands

543

Note amended

Note:

I/O2 and I/O3 are undefined at present.

22.3.3 Bus Timing

Table 22.7 Bus Timing

567

Description amended and notes added

Conditions: V

CC = 5.0 V ± 10%, AVCC = 5.0 V ±10%, AVCC = VCC

±10%, V

SS = AVSS = 0 V, Ta = – 20 to +75°C

Notes: TPC is the set value of the TPC bit in DCR.

The delay time Min values are reference values

(typ).)

22.3.4 Direct Memory

Access Controller

Timing

Table 22.8 Direct

Memory Access

Controller Timing

579

Description amended

Conditions: V

CC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC

±10%, V

SS = AVSS = 0 V, Ta = – 20 to +75°C

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