SH7014 datasheet(100/754 Pages) RENESAS

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5. Exception Processing

Rev.5.00 Sep. 27, 2007 Page 66 of 716

REJ09B0398-0500

5.4.2

Interrupt Priority Level

The interrupt priority order is predetermined. When multiple interrupts occur simultaneously

(overlap), the interrupt controller (INTC) determines their relative priorities and starts up

processing according to the results.

The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest

and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is

always accepted. IRQ interrupts and on-chip peripheral module interrupt priority levels can be set

freely using the INTC's interrupt priority level setting registers A through H (IPRA to IPRH) as

shown in table 5.7. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See

section 6.3.1, Interrupt Priority Registers A to H (IPRA to IPRH), for more information on IPRA

to IPRH.

Table 5.7

Interrupt Priority Order

Type

Priority Level

Comment

NMI

Fixed priority level. Cannot be masked.

IRQ

0 to 15

Set with interrupt priority level setting registers A

through H (IPRA to IPRH).

On-chip peripheral module

0 to 15

Set with interrupt priority level setting registers A

through H (IPRA to IPRH).

5.4.3

Interrupt Exception Processing

When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI

is always accepted, but other interrupts are only accepted if they have a priority level higher than

the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).

When an interrupt is accepted, exception processing begins. In interrupt exception processing, the

CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted

interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set

in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from

the exception processing vector table for the accepted interrupt, that address is jumped to and

execution begins. See section 6.4, Interrupt Operation, for more information on the interrupt

exception processing.

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