SH7014 datasheet(119/754 Pages) RENESAS

119 / 754 page

6. Interrupt Controller (INTC)

Rev.5.00 Sep. 27, 2007 Page 85 of 716

REJ09B0398-0500

6.4

Interrupt Operation

6.4.1

Interrupt Sequence

The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the

operations.

1. The interrupt request sources send interrupt request signals to the interrupt controller.

2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent,

following the priority levels set in interrupt priority level setting registers A to H (IPRA to

IPRH). Lower-priority interrupts are ignored. They are held pending until interrupt requests

designated as edge-detect type are accepted. For IRQ interrupts, however, withdrawal is

possible by accessing the IRQ status register (ISR). See section 6.2.2, IRQ Interrupts, for

details. Interrupts held pending due to edge detection are cleared by a power-on reset. If two of

these interrupts have the same priority level or if multiple interrupts occur within a single

module, the interrupt with the highest default priority or the highest priority within its IPR

setting range (as indicated in table 6.3) is selected.

3. The interrupt controller compares the priority level of the selected interrupt request with the

interrupt mask bits (I3 to I0) in the CPU's status register (SR). If the request priority level is

equal to or less than the level set in I3 to I0, the request is ignored. If the request priority level

is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends

an interrupt request signal to the CPU.

4. The CPU detects the interrupt request sent from the interrupt controller when it decodes the

next instruction to be executed. Instead of executing the decoded instruction, the CPU starts

interrupt exception processing (figure 6.4).

5. SR and PC are saved onto the stack.

6. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in

the status register (SR).

7. The CPU reads the start address of the exception service routine from the exception vector

table for the accepted interrupt, jumps to that address, and starts executing the program there.

This jump is not a delay branch.

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