SH7014 datasheet(130/754 Pages) RENESAS

130 / 754 page

7. Cache Memory (CAC)

Rev.5.00 Sep. 27, 2007 Page 96 of 716

REJ09B0398-0500

7.3

Address Array and Data Array

There is a special cache space for controlling the cache. This space is divided into an address array

and a data array, where addresses (tag address, including valid bit) and data (4-byte line length) for

cache control are recorded. The special cache space is shown in table 7.2. It can be used as on-chip

RAM space when the cache is not being used.

Table 7.2

Special Cache Space

Space Classification

Address

Size

Bus Width

Address array

H'FFFFF000 to H'FFFFF3FF

1 kbyte

32 bits

Data array

H'FFFFF400 to H'FFFFF7FF

1 kbyte

32 bits

7.3.1

Cache Address Array Read/Write Space

The cache address array has a compulsory read/write (figure 7.3).

Address

Upper 22 bits of the address array space address

(22 bits)

⎯

(2 bits)

Entry address

(8 bits)

10 9

Data

⎯

(6 bits)

⎯

(10 bits)

Tag address

(15 bits)

Valid bit (1 bit)

10 9

26 25 24

Figure 7.3 Cache Address Array

Address Array Read: Designates entry address and reads out the corresponding tag address

value/valid bit value.

Address Array Write: Designates entry address and writes the designated tag address value/valid

bit value.

SH7014 Datasheet(PDF) 130 Page - Renesas Technology Corp

SH7014 Datasheet(HTML) 130 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL