7721 datasheet(61/577 Pages) RENESAS

61 / 577 page

CONNECTION WITH EXTERNAL DEVICES

3.4 Hold function

7721 Group User’s Manual

3–14

Fig. 3.4.2 Timing of acceptance of Hold request and termination of Hold state (2)

R/W

ST1

HOLD

ALE

ST0

Bus request (Hold)

Bus request sampling

<When inputting “L” level to HOLD pin while bus is used; when data access is

completed with 1-bus cycle>

q State when inputting “L” level to HOLD pin

8, 16

16 (Access beginning at even address)

External data bus

Data length

External data bus width

Used

Clock

(Note 2)

Floating

Address A

Floating

Data

Address B

External address bus

External address bus /

External data bus

BLE, BHE

Bus in

use

Transfer of

right to use bus

Hold state

Bus in use

When a Hold request is accepted, not a new address but the address

which was output immediately before is output again.

Notes 1: The above diagram shows the case of no Wait.

2: Clock 1 has the same polarity and the same frequency as .

Timing of signals to be input from or output to the external is

ordained on the basis of clock 1.

3: Bus request (Hold) and bus request sampling are internal signals.

(Note 3)

Transfer of

right to use bus

7721 Datasheet(PDF) 61 Page - Renesas Technology Corp

7721 Datasheet(HTML) 61 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL