7721 datasheet(62/577 Pages) RENESAS

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CONNECTION WITH EXTERNAL DEVICES

7721 Group User’s Manual

3–15

3.4 Hold function

Data

R/W

HOLD

ALE

Floating

Address B

Address A

When a Hold request is accepted, not a new address but the address which was output

immediately before is output again.

ST1

ST0

Bus request (Hold)

Bus request sampling

Transfer of right

to use bus

<When inputting “L” level to HOLD pin while bus is used; when data access is

completed with continuous 2-bus cycle>

q State when inputting “L” level to HOLD pin

16 (Access beginning at odd address)

Used

External data bus

Data length

External data bus width

Clock

(Note 2)

Floating

Address A + 1

Data

External address bus /

External data bus

External address bus

BLE, BHE

Bus in use

Hold state

Bus in use

Notes 1: The above diagram shows the case of 2-

access in low-speed running.

2: Clock

has the same polarity and the same frequency as .

Timing of signals to be input from or output to the external is ordained on the basis

of clock

3: Bus request (Hold) and bus request sampling are internal signals.

Floating

(Note 3)

Transfer of right

to use bus

Fig. 3.4.3 Timing of acceptance of Hold request and termination of Hold state (3)

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