7721 datasheet(181/577 Pages) RENESAS

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7721 Group User’s Manual

TIMER B

9–14

9.4 Event counter mode

In this mode, the timer counts an external signal. (Refer to “Table 9.4.1.”) Figure 9.4.1 shows the structures

of the timer Bj mode register and the timer Bj register in the event counter mode.

Table 9.4.1 Specifications of event counter mode

Specifications

•External signal input to the TBjIN pin

•The count source’s valid edge can be selected from the falling edge,

the rising edge, and both of the falling and rising edges by software.

•Countdown

•When a counter underflow occurs, reload register’s contents are reloaded,

and counting continues.

When the count start bit is set to “1.”

When the count start bit is cleared to “0.”

When a counter underflow occurs.

Count source input

Counter value can be read out.

q While counting is stopped

When a value is written to the timer Bj register, it is written to both

of the reload register and counter.

q While counting is in progress

When a value is written to the timer Bj register, it is written only to

the reload register. (Transferred to the counter at the next reload

time.)

(n + 1)

n : Timer Bj register’s set value

Item

Count source

Count operation

Division ratio

Count start condition

Count stop condition

Interrupt request occurrence timing

TBjIN pin’s function

Read from timer Bj register

Write to timer Bj register

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