4513 datasheet(130/210 Pages) RENESAS

130 / 210 page

APPLICATION

2.3 Timers

2-27

4513/4514 Group User’s Manual

2.3.2 Related registers

(1)

Interrupt control register V1

The timer 1 interrupt enable bit is assigned to bit 2, and the timer 2 interrupt enable bit is assigned

to bit 3.

Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction

can be used to transfer the contents of register V1 to register A.

Table 2.3.1 shows the interrupt control register V1.

Table 2.3.1 Interrupt control register V1

Interrupt control register V1

at reset : 00002

at RAM back-up : 00002

R/W

Interrupt disabled (SNZT2 instruction is valid)

Interrupt enabled (SNZT2 instruction is invalid)

Interrupt disabled (SNZT1 instruction is valid)

Interrupt enabled (SNZT1 instruction is invalid)

Interrupt disabled (SNZ1 instruction is valid)

Interrupt enabled (SNZ1 instruction is invalid)

Interrupt disabled (SNZ0 instruction is valid)

Interrupt enabled (SNZ0 instruction is invalid)

Timer 2 interrupt enable bit

Timer 1 interrupt enable bit

External 1 interrupt enable bit

External 0 interrupt enable bit

V13

V12

V11

V10

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: When timer is used, V11 and V10 are not used.

(2)

Interrupt control register V2

The timer 3 interrupt enable bit is assigned to bit 0, and the timer 4 interrupt enable bit is assigned

to bit 1.

Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction

can be used to transfer the contents of register V2 to register A.

Table 2.3.2 shows the interrupt control register V2.

Table 2.3.2 Interrupt control register V2

Interrupt control register V2

at reset : 00002

at RAM back-up : 00002

R/W

Interrupt disabled (SNZSI instruction is valid)

Interrupt enabled (SNZSI instruction is invalid)

Interrupt disabled (SNZAD instruction is valid)

Interrupt enabled (SNZAD instruction is invalid)

Interrupt disabled (SNZT4 instruction is valid)

Interrupt enabled (SNZT4 instruction is invalid)

Interrupt disabled (SNZT3 instruction is valid)

Interrupt enabled (SNZT3 instruction is invalid)

Serial I/O interrupt enable bit

A-D interrupt enable bit

Timer 4 interrupt enable bit

Timer 3 interrupt enable bit

V23

V22

V21

V20

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: When timer is used, V22 and V23 are not used.

4513 Datasheet(PDF) 130 Page - Renesas Technology Corp

4513 Datasheet(HTML) 130 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL