CS4350 datasheet(34/41 Pages) CIRRUS

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DS691F1

CS4350

Soft Ramp and Zero Cross

Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-

ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will

occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample

rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored

and implemented for each channel.

8.6.2

Soft Volume Ramp-Up after Error (RMP_UP) Bit 5

Function:

When set to 1 (default), an un-mute will be performed after executing a filter mode change, after LRCK is

lost, and after changing the Functional Mode. This un-mute is affected, similar to attenuation changes, by

the Soft and Zero Cross bits in the Volume and Mixing Control register.

When set to 0, an immediate un-mute is performed in these instances.

Note:

For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.

8.6.3

Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4

Function:

When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is

affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control

When set to 0, an immediate mute is performed prior to executing a filter mode change.

Note:

For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.

8.6.4

Interpolation Filter Select (FILT_SEL) Bit 2

Function:

When set to 0 (default), the Interpolation Filter has a fast roll off.

When set to 1, the Interpolation Filter has a slow roll off.

The specifications for each filter can be found in the ”Combined Interpolation & On-Chip Analog Filter Re-

sponse” on page 12, and response plots can be found in Figures 25 through 30.

8.7

Misc. Control - Register 08h

8.7.1

Power Down (PDN) Bit 7

Function:

When set to 1 the entire device will enter a low-power state and the contents of the control registers will

be retained. The power-down bit defaults to ‘0’ on power-up.

543

PDN

Reserved

FREEZE

POPG_EN

RMCK_CTRL1 RMCK_CTRL0 R_SELECT1

R_SELECT0

010

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