AT89C5131A-RDTUM datasheet(133/188 Pages) ATMEL

133 / 188 page

133

4337K–USB–04/08

AT89C5130A/31A-M

21.7.2

STALL Handshake

This function is only available for Control, Bulk, and Interrupt endpoints.

The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake

at the next request of the Host on the endpoint selected with the UEPNUM register. The

RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first reset to 0. The bit

STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an inter-

rupt if enabled.

The firmware will clear the STALLRQ and STLCRC bits after each STALL sent.

The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on

a CONTROL type endpoint.

Important note: when a Clear Halt Feature occurs for an endpoint, the firmware will reset this

endpoint using the UEPRST register in order to reset the data toggle management.

21.7.3

Start of Frame Detection

The SOFINT bit in the USBINT register is set when the USB controller detects a Start of Frame

PID. This triggers an interrupt if enabled. The firmware will clear the SOFINT bit to allow the next

Start of Frame detection.

21.7.4

Frame Number

When receiving a Start of Frame, the frame number is automatically stored in the UFNUML and

UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start of

Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The UFNUML and UFNUMH

registers are automatically updated when receiving a new Start of Frame.

21.7.5

Data Toggle Bit

The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted by the

USB controller and cleared by hardware when a DATA1 packet is received and accepted by the

USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST

For Control endpoints, each SETUP transaction starts with a DATA0 and data toggling is then

used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Sta-

tus stage completes the data transfer with a DATA1 (for a control read transfer).

For Isochronous endpoints, the device firmware will ignore the data-toggle.

21.8

Suspend/Resume Management

21.8.1

Suspend

The Suspend state can be detected by the USB controller if all the clocks are enabled and if the

USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for

more than 3 ms. This triggers a USB interrupt if enabled.

In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop

the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active.

The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new

suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSP-

CLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake-

up event is detected.

AT89C5131A-RDTUM Datasheet(PDF) 133 Page - ATMEL Corporation

AT89C5131A-RDTUM Datasheet(HTML) 133 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL