AT89C5131A-RDTUM datasheet(134/188 Pages) ATMEL

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134

4337K–USB–04/08

AT89C5130A/31A-M

The stop of the 48 MHz clock from the PLL should be done in the following order:

Clear suspend interrupt bit in USBINT (required to allow the USB pads to enter power

down mode).

Enable USB resume interrupt.

Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit

in the USBCON register.

Disable the PLL by clearing the PLLEN bit in the PLLCON register.

Make the CPU core enter power down mode by setting PDOWN bit in PCON.

21.8.2

Resume

When the USB controller is in Suspend state, the Resume detection is active even if all the

clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by

hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled.

This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is

then executed. The firmware will first enable the 48 MHz generation and then reset to 0 the

SUSPCLK bit in the USBCON register if needed.

The firmware has to clear the SPINT bit in the USBINT register before any other USB operation

in order to wake up the USB controller from its Suspend mode.

The USB controller is then re-activated.

Figure 21-11. Example of a Suspend/Resume Management

21.8.3

Upstream Resume

A USB device can be allowed by the Host to send an upstream resume for Remote Wake Up

purpose.

USB Controller Init

Detection of a SUSPEND State

SPINT

Set SUSPCLK

Disable PLL

microcontroller in Power-down

Detection of a RESUME State

WUPCPU

Enable PLL

Clear SUSPCLK

Clear WUPCPU Bit

Clear SPINT

AT89C5131A-RDTUM Datasheet(PDF) 134 Page - ATMEL Corporation