AT89C5131A-RDTUM datasheet(130/188 Pages) ATMEL

130 / 188 page

130

4337K–USB–04/08

AT89C5130A/31A-M

The firmware will never write more bytes than supported by the endpoint FIFO.

21.5

Control Transactions

21.5.1

Setup Stage

The DIR bit in the UEPSTAX register will be at 0.

Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP

bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate

that an Out packet with a Setup PID has been received on the Control endpoint. When the

RXSETUP bit has been set, all the other bits of the UEPSTAX register are cleared and an inter-

rupt is triggered if enabled.

The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing

the RXSETUP bit to free the endpoint FIFO for the next transaction.

21.5.2

Data Stage: Control Endpoint Direction

The data stage management is similar to Bulk management.

A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All

other endpoint types are managed as half-duplex endpoint: IN or OUT. The firmware has to

specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX regis-

ter.

The firmware has to use the DIR bit before data IN in order to meet the data-toggle

requirements:

• If the data stage consists of INs,

the firmware has to set the DIR bit in the UEPSTAX register before writing into the FIFO and

sending the data by setting to 1 the TXRDY bit in the UEPSTAX register. The IN transaction

is complete when the TXCMPL has been set by the hardware. The firmware will clear the

TXCMPL bit before any other transaction.

• If the data stage consists of OUTs,

the firmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware when a new

valid packet has been received on the endpoint. The firmware must read the data stored into

the FIFO and then clear the RXOUTB0 bit to reset the FIFO and to allow the next transaction.

To send a STALL handshake, see “STALL Handshake” on page 133.

21.5.3

Status Stage

The DIR bit in the UEPSTAX register will be reset at 0 for IN and OUT status stage.

The status stage management is similar to Bulk management.

• For a Control Write transaction or a No-Data Control transaction, the status stage consists of

a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions in Standard Mode” on page

128). To send a STALL handshake, see “STALL Handshake” on page 133.

• For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see

“Bulk/Interrupt OUT Transactions in Standard Mode” on page 126).

AT89C5131A-RDTUM Datasheet(PDF) 130 Page - ATMEL Corporation

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