Application

BASIC INTERFACE OPERATION

All I/O to and from the TWSI core is synchronous to the system clock, CLK.

Before any operation of the MC-TWSI core, the ENABLE must first be asserted. This must be done via a register on the host interface.

For a TWSI master to initiate a transaction on the bus, the host sets up the ADDR_IN, DATA_IN and TWSI_CMD ports and strobes the START input for one clock and

performs other operations until either REQ_DATA (in the case of a write) or DATA_VLD (in the case of a read) is asserted. Also, the SLAVE_TIMEOUT (STATUS[0])

and BUSLOSS (STATUS[1]) bits should be polled in case the slave does not respond or the master loses arbitration. The BUSLOSS status bit will be asserted if the

interface lost the bus to another master before completion of the cycle. The SLAVE_TIMEOUT bit will be asserted if the slave does not respond with a NACK when

required. For either of these error conditions, the host must retry the current cycle by strobing START. Note that for burst operations the host is responsible for writing

the incremented address into the ADDRESS Register before retrying the operation.

HOST WRITE OPERATION

The following figure shows how the microprocessor interface connects to the internal control registers:

Figure 6: Host Write Register Interface

On the rising edge of CLK, the values on DATA_IN[7:0] and ADDR_IN[6:0] and TWSI_CMD[2:0] is clocked into their registers when START is strobed.

Figure 7: Input Register Timing

Notice in Figure 7 that START acts as the write enable for the registers. Also notice that when CLK samples START asserted, the STATUS bits are cleared on the

next rising edge of CLK.

CLK

MDS2108a

DATA_IN[7:0]

ADDR_IN[6:0]

START

Valid

"000000"

Old Value

STATUS

Valid

TWSI_CMD[2:0]

Valid

8

D Q

CE

DATA_IN[7:0]

START

data_in_r[7:0]

7

D Q

CE

addr_in_r[6:0]

3

D Q

CE

twsi_cmd_r[2:0]

CLK

MDS2105

ADDR_IN[6:0]

TWSI_CMD[2:0]