Functional Description

The diagram on the first page shows the Block Diagram of the MC-ACT-16550 Core. The core is partitioned into modules. These modules are described below.

INTERFACE CONTROL LOGIC

The core is configured via a configuration vector (CFG[127:0]). This vector contains information required for proper operation of the core. The command vector input

(TWSI_CMD[2:0]) is used to instruct the core what operation to perform. The contents of the input and output vectors are as follows:

Configuration Vector

Applicable to the following core configurations:

Master-Only

Master-Slave

Slave-Only

Yes

Yes

Yes

The bits of the Configuration Vector are defined as follows:

Configuration Bits

Description

CFG[6:0]

TWSI Slave’s Own Address

CFG[7]

Reserved

CFG[19:8]

SCL BusFree (arbitration) Timer Value for Standard Speed

CFG[31:20]

SCL HI Timer Value for Standard Speed

CFG[43:32]

SCL LO Timer Value for Standard Speed

CFG[45:44]

TWSI Mode (Master-Only, Slave-Only, Master-Slave)

CFG[46]

Enable the SCL Glitch Filters

CFG[47]

Enable two extra CLK periods of hold time on SDA from the falling edge of SCL.

CFG[48]

Enable General Call Addressing

CFG[60:49]

SCL BusFree (arbitration) Timer Value for Fast Speed

CFG[72:61]

SCL HI Timer Value for Fast Speed

CFG[84:73]

SCL LO Timer Value for Fast Speed

CFG[127:85]

Reserved

Table 1: Configuration Vector

Command Vector

Applicable to the following core configurations:

Master-Only

Master-Slave

Slave-Only

Yes

Yes

Undefined

The bits in this vector are defined as follows:

2

1

0

RESTART

STOP

READ

Figure 1: Command Vector

These three bits of the command vector control the operation performed on the serial interface. The READ bit determines if the operation will be a read (high) or a

write (low). The STOP bit will determine if the cycle will stop at the end of the data cycle, or continue on to a burst. The REPEATED START bit will cause the genera-

tion of a repeated start protocol.