AX2000-1CS896M datasheet(75/226 Pages) ACTEL

75 / 226 page

Axcelerator Family FPGAs

v2.7

2-61

The HM and CM modules can select between:

•

The HCLK or CLK source respectively

•

A local signal routed on generic routing resources

This

allows

each

core

tile

have

eight

clocks

independent of the other core tiles in the device.

Both HCLK and CLK are segmentable, meaning that

individual branches of the global resource can be used

independently.

Like the HM and CM modules, the HD and RD modules

can select between:

•

The HCLK or CLK source from the HM or CM

module respectively

•

A local signal routed on generic routing resources

The AX architecture is capable of supporting a large

number of local clocks – 24 segments per HCLK driving

north-south and 28 segments per CLK driving east-west

per core tile.

Actel's

Designer

software’s

place-and-route

takes

advantage of the segmented clock structure found in

Axcelerator devices by turning off any unused clock

segments. This results in not only better performance but

also lower power consumption.

Global Resource Access Macros

Global resources can be driven by one of three sources:

external pad(s), an internal net, or the output of a PLL.

These connections can be made by using one of three

types of macros: CLKBUF, CLKINT, and PLLCLK.

CLKBUF and HCLKBUF

CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from

external pads. These macros can be used either

generically or with the specific I/O standard desired

(e.g.

CLKBUF_LVCMOS25,

HCLKBUF_LVDS,

etc.)

(Figure 2-42).

Package pins CLKEP and CLKEN are associated with

CLKE; package pins HCLKAP and HCLKAN are

associated with HCLKA, etc.

Note that when CLKBUF (HCLKBUF) is used with a

single-ended I/O standard, it must be tied to the P-

pad of the CLK (HCLK) package pin. In this case, the

CLK (HCLK) N-pad can be used for user signals.

CLKINT and HCLKINT

CLKINT (HCLKINT) is used to access the CLK (HCLK)

resource internally from the user signals (Figure 2-43).

PLLRCLK and PLLHCLK

PLLRCLK (PLLHCLK) is used to drive global resource

CLK (HCLK) from a PLL (Figure 2-44).

Using Global Resources with PLLs

Each global resource has an associated PLL at its root. For

example, PLLA can drive HCLKA, PLLE can drive CLKE, etc.

(Figure 2-45 on page 2-62).

In addition, each clock pin of the package can be used to

drive either its associated global resource or PLL. For

example, package pins CLKEP and CLKEN can drive either

the RefCLK input of PLLE or CLKE.

There are two macros required when interfacing the

embedded PLLs with the global resources: PLLINT and PLLOUT.

PLLINT

This macro is used to drive the RefCLK input of the PLL

internally from user signals.

PLLOUT

This macro is used to connect either the CLK1 or CLK2

output of a PLL to the regular routing network (Figure 2-

46 on page 2-62).

Figure 2-42 • CLKBUF and HCLKBUF

CLKBUF

HCLKBUF

Clock

Network

Figure 2-43 • CLKINT and HCLKINT

Figure 2-44 • PLLRCLK and PLLHCLK

CLKINT

HCLKINT

Clock

Network

Logic

PLLRCLK

PLLHCLK

Clock

Network

CLK1

CLK2

RefCLK

PLL

AX2000-1CS896M Datasheet(PDF) 75 Page - Actel Corporation

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