AX2000-1CS896M datasheet(43/226 Pages) ACTEL

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Axcelerator Family FPGAs

v2.7

2-29

1.5V LVCMOS (JESD8-11)

Low-Voltage Complementary Metal-Oxide Semiconductor for 1.5V is an extension of the LVCMOS standard (JESD8-5)

used for general-purpose 1.5V applications. It uses a 3.3V tolerant CMOS input buffer and a push-pull output buffer.

AC Loadings

Timing Characteristics

Table 2-28 • DC Input and Output Levels

VIL

VIH

VOL

VOH

IOL

IOH

Min,V

Max,V

Min,V

Max,V

Min,V

-0.5

0.35VCCI

0.65VCCI

3.6

0.4

VCCI-0.4

8mA

-8mA

Table 2-29 • AC Test Loads

Table 2-30 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

Cload (pF)

1.5

0.5VCCI

N/A

* Measuring Point = Vtrip

R to VCCI for tplz/tpzl

R to GND for tphz/tpzh

35 pF for tpzh/tpzl

5 pF for tphz/tplz

Test Point

35 pF

for tristate

R=1k

for tpd

Table 2-31 • 1.5V LVCMOS I/O Module

Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 1.4V, TJ = 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

LVCMOS15 (JESD8-11) I/O Module Timing

tDP

Input Buffer

3.63

4.14

4.87

tPY

Output Buffer

6.02

6.86

8.07

tICLKQ

Clock-to-Q for the I/O input register

0.67

0.77

0.90

tOCLKQ

Clock-to-Q for the IO output register and the I/O

enable register

0.67

0.77

0.90

tSUD

Data Input Set-Up

0.23

0.27

0.31

tSUE

Enable Input Set-Up

0.26

0.30

0.35

tHD

Data Input Hold

0.00

tHE

Enable Input Hold

0.00

tCPWHL

Clock Pulse Width High to Low

0.43

0.48

0.57

tCPWLH

Clock Pulse Width Low to High

0.45

0.51

0.60

tWASYN

Asynchronous Pulse Width

0.43

0.48

0.57

tREASYN

Asynchronous Recovery Time

0.10

tHASYN

Asynchronous Removal Time

0.00

tCLR

Asynchronous Clear-to-Q

0.23

0.27

0.31

tPRESET

Asynchronous Preset-to-Q

0.23

0.27

0.31

AX2000-1CS896M Datasheet(PDF) 43 Page - Actel Corporation

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