AX2000-1CS896M datasheet(81/226 Pages) ACTEL

81 / 226 page

Axcelerator Family FPGAs

v2.7

2-67

Special PLL Macros

Table 2-83 shows the macros used to connect the RefCLK input and CLK1 and CLK2 outputs using the different routing

resources.

Table 2-83 • PLL Special Macros

Macro Name

Usage

PLLINT

Connects RefCLK to a regular routed net or a pad.

PLLRCLK

Connects CLK1 or CLK2 to the CLK network.

PLLHCLK

Connects CLK1 or CLK2 to the HCLK network.

PLLOUT

Connects CLK1 or CLK2 to a regular routed net.

Table 2-84 • Electrical Specifications

Parameter

Value

Notes

Frequency Ranges

Reference Frequency (min.)

14 MHz

Lowest input frequency

Reference Frequency (max.)

200 MHz

Highest input frequency

OSC Frequency (min.)

20 MHz

Lowest output frequency

OSC Frequency (max.)

1 GHz

Highest output frequency

Jitter

Long-Term Jitter (max.)

Percentage of period, low reference clock frequencies

Long-Term Jitter (max.)

100ps

High reference clock frequencies

Short-Term Jitter (max.)

50ps+1%

Percentage of output frequency

Acquisition Time (lock) from Cold Start

Acquisition Time (max.)*

400 cycles

Period of low reference clock frequencies

Acquisition Time (max.)*

1.5

μs

High reference clock frequencies

Power Consumption

Analog Supply Current (low freq.)

200

μA

Current at minimum oscillator frequency

Analog Supply Current (high freq.)

200

μA

Frequency-dependent current

Digital Supply Current (low freq.)

0.5

μA/MHz

Current at maximum oscillator frequency, unloaded

Digital Supply Current (high freq.)

μA/MHz

Frequency-dependent current

Duty Cycle

Minimum Output Duty Cycle

45%

Maximum Output Duty Cycle

55%

Note: *The lock bit remains Low until RefCLK reaches the minimum input frequency.

AX2000-1CS896M Datasheet(PDF) 81 Page - Actel Corporation

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