AX2000-1CS896M datasheet(28/226 Pages) ACTEL

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Axcelerator Family FPGAs

2- 14

v2.7

I/O Clusters

Each I/O cluster incorporates two I/O modules, four RX

modules and two TX modules, and a buffer module. In

turn, each I/O module contains one Input Register

(InReg), one Output Register (OutReg), and one Enable

Using an I/O Register

To access the I/O registers, registers must be instantiated

in the netlist and then connected to the I/Os. Usage of

each I/O register (register combining) is individually

controlled and can be selected/deselected using the

PinEditor tool in Actel's Designer software. I/O register

combining can also be controlled at the device level,

affecting all I/Os. Please note, the I/O register option is

deselected by default in any given design.4

In addition, Designer software provides a global option to

enable/disable the usage of registers in the I/Os. This option

is design-specific. The setting for each individual I/O

overrides this global option. Furthermore, the global set

fuse option in the Designer software, when checked, causes

all I/O registers to output logic High at device power-up.

Using the Weak Pull-Up and Pull-Down

Circuits

Each Axcelerator I/O comes with a weak pull-up/down

circuit (on the order of 10 k

Ω). I/O macros are provided

for combinations of pull up/down for LVTTL, LVCMOS

(2.5V, 1.8V, and 1.5V) standards. These macros can be

instantiated if a keeper circuit for any input buffer is

required.

Customizing the I/O

•

A five-bit programmable input delay element is

associated with each I/O. The value of this delay is

set on a bank-wide basis (Table 2-14 on page 2-15).

It is optional for each input buffer within the bank

(i.e. the user can enable or disable the delay

element for the I/O). When the input buffer drives a

Figure 2-5 • I/O Cluster Interface

EnReg

DIN YOUT

DCIN

OutREg

DIN YOUT

InReg

I/O CLUSTER

OEP

UOP

UIP

programmable delay

slew rate

I/O

OEN

UON

UIN

drive strength

P PAD

N PAD

routed input track

output track

routed input track

output track

routed input track

output track

EnReg

DIN YOUT

DCIN

OutREg

DIN YOUT

InReg

routed input track

output track

programmable delay

slew rate

I/O

drive strength

VREF

4. Please note that register combining for multi fanout nets is not supported.

AX2000-1CS896M Datasheet(PDF) 28 Page - Actel Corporation

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