LTM9002 datasheet(24/28 Pages) LINER

24 / 28 page

LTM9002

9002f

APPLICATIONS INFORMATION

Clock Duty Cycle Stabilizer

An optional clock duty cycle stabilizer circuit ensures high

performance even if the input clock has a non 50% duty

cycle. Using the clock duty cycle stabilizer is recommended

for most applications. To use the clock duty cycle stabilizer,

the MODE pin should be connected to 1/3VDD or 2/3VDD

using external resistors.

This circuit uses the rising edge of the CLK pin to sample

the analog input. The falling edge of CLK is ignored and

the internal falling edge is generated by a phase-locked

loop. The input clock duty cycle can vary from 40% to

60% and the clock duty cycle stabilizer will maintain a

constant 50% internal duty cycle. If the clock is turned off

for a long period of time, the duty cycle stabilizer circuit

will require a hundred clock cycles for the PLL to lock

onto the input clock.

For applications where the sample rate needs to be changed

quickly, the clock duty cycle stabilizer can be disabled. If

the duty cycle stabilizer is disabled, care should be taken to

make the sampling clock have a 50% (±5%) duty cycle.

DIGITAL OUTPUTS

Table 6 shows the relationship between the analog input

voltage, the digital data bits, and the overﬂow bit. Note that

OF is high when an overﬂow or underﬂow has occurred

on either channel A or channel B.

Table 6. Output Codes vs Input Voltage, 100mV Input Span

IN+ – IN–

(SENSE = VDD)OF

D13 - D0

(OFFSET BINARY)

D13 - D0

(2’S COMPLEMENT)

≥ 50mV

11 1111 1111 1111

11 1111 1111 1110

01 1111 1111 1111

01 1111 1111 1110

0.000000V

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

01 1111 1111 1110

00 0000 0000 0001

00 0000 0000 0000

11 1111 1111 1111

11 1111 1111 1110

≤ –50mV

00 0000 0000 0001

00 0000 0000 0000

10 0000 0000 0001

10 0000 0000 0000

Digital Output Modes

Figure 12 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, isolated

from the ADC power and ground. The additional N-channel

transistor in the output driver allows operation down to

low voltages. The internal resistor in series with the output

makes the output appear as 50Ω to external circuitry and

may eliminate the need for external damping resistors.

As with all high speed/high resolution converters the digital

output loading can affect the performance. The digital

outputs of the ADC should drive a minimal capacitive load

to avoid possible interaction between the digital outputs

and sensitive input circuitry. For full-speed operation, the

capacitive load should be kept under 10pF.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

Figure 12. Digital Output Buffer

LTM9002

9002 F12

OVDD

VDD

0.1μF

43Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

LTM9002 Datasheet(PDF) 24 Page - Linear Technology

LTM9002 Datasheet(HTML) 24 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL