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LTM9002

9002f

APPLICATIONS INFORMATION

Data Format

Using the MODE pin, the ADC parallel digital output can

be selected for offset binary or 2’s complement format.

Note that MODE controls both channel A and channel B.

Connecting MODE to GND or 1/3 VDD selects straight

binary output format. Connecting MODE to 2/3 VDD or

VDD selects 2’s complement output format. An external

resistive divider can be used to set the 1/3 VDD or 2/3

VDD logic values. Table 7 shows the logic states for the

MODE pin.

Table 7. MODE Pin Function

MODE PIN

OUTPUT FORMAT

CLOCK DUTY CYCLE

STABILIZER

Straight Binary

Off

1/3VDD

Straight Binary

2/3VDD

2’s Complement

VDD

2’s Complement

Off

Overﬂow Bit

For LTM9002-AA, when OF outputs a logic high the con-

verter is either overranged or underranged on channel A

or channel B. Note that both channels share a common

OF pin. OF is disabled when channel A is in sleep or nap

mode. For LTM9002-LA, OFA and OFB indicate either

condition for the respective channel.

Output Clock

The LTM9002-AA has a delayed version of the CLKB input

available as a digital output, CLKOUT. The falling edge of

the CLKOUT pin can be used to latch the digital output

data. CLKOUT is disabled when channel B is in sleep or

nap mode.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same supply that powers the logic being driven.

For example, if the converter drives a DSP powered by a

1.8V supply, then OVDD should be tied to that same 1.8V

supply.

OVDD can be powered with any voltage from 500mV up to

3.6V, independent of VDD. OGND can be powered with any

voltage from GND up to 1V and must be less than OVDD.

The logic outputs will swing between OGND and OVDD.

Output Enable

The outputs may be disabled with the output enable pin,

OE. OE high disables all data outputs including OF. The

data access and bus relinquish times are too slow to allow

the outputs to be enabled and disabled during full-speed

operation. The output Hi-Z state is intended for use during

test or initialization. Channels A and B have independent

output enable pins (OEA, OEB.)

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes

to conserve power. Connecting ADCSHDN to GND results

in normal operation. Connecting ADCSHDN to VDD and

OE to VDD results in sleep mode, which powers down all

circuitry including the reference and the ADC typically

dissipates 1mW. When exiting sleep mode, it will take

700μs to 1ms for the output data to become valid because

the reference capacitors have to recharge and stabilize.

Connecting ADCSHDN to VDD and OE to GND results in

nap mode and the ADC typically dissipates 30mW. In nap

mode, the on-chip reference circuit is kept on, so that

recovery from nap mode is faster than that from sleep

mode, typically taking 100 clock cycles. In both sleep

and nap modes, all digital outputs are disabled and enter

the Hi-Z state.

Channels A and B have independent ADCSHDN pins

(ADCSHDNA, ADCSHDNB.) Channel A is controlled by

ADCSHDNA and OEA, and channel B is controlled by

ADCSHDNB and OEB. The nap, sleep and output enable

modes of the two channels are completely independent,

so it is possible to have one channel operating while the

other channel is in nap or sleep mode.

Digital Output Multiplexer

The digital outputs of the ADC can be multiplexed onto a

single data bus. The MUX pin is a digital input that swaps

the two data busses. If MUX is high, channel A comes

out on DAx; channel B comes out on DBx. If MUX is low,

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