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MC33596FCE/R2 Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc |
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MC33596FCE/R2 Datasheet(HTML) 23 Page - Freescale Semiconductor, Inc |
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23 / 70 page ![]() Receive Mode MC33596 Data Sheet, Rev. 4 Freescale Semiconductor 23 • At the LNA output, the LNA AGC control voltage is used to monitor input signals in the range –50 dBm to –20 dBm. Therefore, the logarithmic amplifier provides information relative to the in-band signal, whereas the LNA AGC voltage senses the input signal over a wider band. The RSSI information given by the logarithmic amplifier is available in: • Analog form on pin RSSIOUT • Digital form in the four least significant bits of the status register RSSI The information from the LNA AGC is available in digital form in the four most significant bits of status register RSSI. The whole content of status register RSSI provides 2 ¥ 4 bits of RSSI information about the incoming signal (see Section 16.6, “RSSI Register”). Figure 15 shows a simplified block diagram of the RSSI function. The quasi peak detector (D1, R1, C1) has a charge time of about 20 μs to avoid sensitivity to spikes. R2 controls the decay time constant of about 5 ms to allow efficient smoothing of the OOK modulated signal at low data rates. This time constant is useful in continuous mode when S2 is permanently closed. To allow high-speed RSSI updating in peak pulse measurement, a discharge circuit (S1) is required to reset the measured voltage and to allow new peak detection. Figure 15. RSSI Simplified Block Diagram S2 is used to sample the RSSI voltage to allow peak pulse measurement (S2 used as sample and hold), or to allow continuous transparent measurement (S2 continuously closed). The 4-bit analog-to-digital convertor (ADC) is based on a flash architecture. The conversion time is 16 × Tdiglck. As a single convertor is used for the two analog signals, the RSSI register content is updated on a 32 × Tdigclk timebase. If RSSIE is reset, the whole RSSI module is switched off, reducing the current consumption. The output buffer connected to RSSIOUT is set to high impedance. Σ RSSIOUT ADC RSSI Register MSB LSB IF Filter Output LNA AGC Out S1 S2 R2 R1 C1 D1 C2 |
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