13892 datasheet(41/75 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages.

SW4OUT

Switcher 4 output. Buck switcher for external memory and

peripherals.

GNDSW4

Ground for switcher 4.

DVS1 AND DVS2

Switcher 1 and 2 DVS input pins. Provided for pin

controlled DVS on the buck switchers targeted for processor

core supplies. The DVS pins may be reconfigured for

Switcher Increment / Decrement (SID) mode control. When

transitioning from one voltage to another, the output voltage

slope is controlled in steps of 25 mV per time step. These

pins must be set high in order for the DVS feature to be

enabled for each of switchers 1 or 2, or low to disable it.

SWBSTIN

Switcher BST input. The 2.2

μH switcher BST inductor

must be connected here.

SWBSTOUT

Power supply for gate driver for the internal power NMOS

that charges SWBST inductor. It must be connected to BP.

SWBSTFB

Switcher BST feedback. When SWBST is configured to

supply the UVBUS pin in OTG mode the feedback will be

switched to sense the UVBUS pin instead of the SWBSTFB

pin.

GNDSWBST

Ground for switcher BST.

REGULATORS

VINIOHI

Input of VIOHI regulator. Connect this pin to BP in order to

supply VIOHI regulator.

VIOHI

Output regulator for high voltage IO. Fixed 2.775 V output

for high voltage level interface.

VINPLL AND VINDIG

The input of the regulator for processor PLL and Digital

regulators respectively. VINDIG and VINPLL can be

connected to either BP or a 1.8 V switched mode power

supply rail, such as from SW4 for the two lower set points of

each regulator (the 1.2 and 1.25 V output for VPLL, and 1.05

and 1.25 V output for VDIG). In addition, when the two upper

set points are used (1.50 and 1.8V outputs for VPLL, and

1.65 and 1.8V for VDIG), they can be connected to either BP

or a 2.2V nominal external switched mode power supply rail,

to improve power dissipation.

VPLL

Output of regulator for processor PLL. Quiet analog supply

(PLL, GPS).

VDIG

Output regulator Digital. Low voltage digital (DPLL, GPS).

VVIDEODRV

Drive output for VVIDEO external PNP transistor.

VVIDEO

Output regulator TV DAC. This pin must be connected to

the collector of the external PNP transistor of the VVIDEO

regulator.

VINAUDIO

Input regulator VAUDIO. Typically connected to BP.

VAUDIO

Output regulator for audio supply.

VINUSB2

Input regulator VUSB2. This pin must always be

connected to BP even if the regulators are not used by the

application.

VUSB2

Output regulator for powering USB PHY.

VINCAMDRV

1. Input regulator camera using internal PMOS FET.

Typically connected to BP.

2. Drive output regulator for camera voltage using external

PNP device. In this case, this pin must be connected to the

base of the PNP in order to drive it.

VCAM

Output regulator for the camera module. When using an

external PNP device, this pin must be connected to its

collector.

VSDDRV

Drive output for the VSD external PNP transistor.

VSD

Output regulator for multi-media cards such as micro SD,

RS-MMC.

VGEN1DRV

Drive output for the VGEN1 external PNP transistor.

13892 Datasheet(PDF) 41 Page - Freescale Semiconductor, Inc

13892 Datasheet(HTML) 41 Page - Freescale Semiconductor, Inc

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