AT91SAM7X512 datasheet(41/687 Pages) ATMEL

41 / 687 page

6120H–ATARM–17-Feb-09

AT91SAM7X512/256/128 Preliminary

Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32-

bit physical register in all processor modes. They are general-purpose registers, with no special

uses managed by the architecture, and can be used wherever an instruction allows a general-

purpose register to be specified.

Registers R8 to R14 are banked registers. This means that each of them depends on the current

mode of the processor.

11.2.4.1

Modes and Exception Handling

All exceptions have banked registers for R14 and R13.

After an exception, R14 holds the return address for exception processing. This address is used

to return after the exception is processed, as well as to address the instruction that caused the

exception.

R13 is banked across exception modes to provide each exception handler with a private stack

pointer.

The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin with-

out having to save these registers.

Table 11-1.

ARM7TDMI ARM Modes and Registers Layout

User and

System Mode

Supervisor

Mode

Abort Mode

Undefined

Mode

Interrupt

Mode

Fast Interrupt

Mode

R8_FIQ

R9_FIQ

R10

R10_FIQ

R11

R11_FIQ

R12

R12_FIQ

R13

R13_SVC

R13_ABORT

R13_UNDEF

R13_IRQ

R13_FIQ

R14

R14_SVC

R14_ABORT

R14_UNDEF

R14_IRQ

R14_FIQ

CPSR

SPSR_SVC

SPSR_ABORT

SPSR_UNDEF

SPSR_IRQ

SPSR_FIQ

Mode-specific banked registers

AT91SAM7X512 Datasheet(PDF) 41 Page - ATMEL Corporation

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