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AT697F Datasheet(PDF) 123 Page - ATMEL Corporation

Part # AT697F
Description  Rad-Hard 32 bit SPARC V8 Processor
PDF  155 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT697F Datasheet(HTML) 123 Page - ATMEL Corporation

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AT697F ADVANCE INFORMATION
123
7703C–AERO–6/09
10
bz
Break on error traps
If set, will force the processor into debug mode on all except the following traps: priviledged_instruction,
fpu_disabled, window_overflow, window_underflow, asynchronous_interrupt, ticc_trap.
9
bx
Break on trap
If set, will force the processor into debug mode when any trap occurs.
8
bd
Break on DSU breakpoint
If set, will force the processor to debug mode when an DSU breakpoint is hit.
7
bn
Break now
Force processor into debug mode. If cleared, the processor will resume execution.
6
bs
Break on S/W breakpoint
If set, debug mode will be forced when an breakpoint instruction (ta 1) is executed
5
bw
Break on IU watchpoint
If set, debug mode will be forced on a IU watchpoint (trap 0xb).
4
be
Break on error
if set, will force the processor to debug mode when the processor would have entered error condition (trap in
trap).
3
ft
Freeze timers
If set, the scaler in the LEON timer unit will be stopped during debug mode to preserve the time for the software
application.
2
bt
Break on trace
If set, will generate a DSU break condition on trace freeze.
1
dm
Delay counter mode
In mixed tracing mode, setting this bit will cause the delay counter to decrement on AHB traces. If reset, the
delay counter will decrement on instruction traces
0
te
Trace enable.
Enables the trace buffer.
Table 116. DSU UART Status Register - DSUUS
Address = 0x800000C4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
fe
ov
th
ts
dr
r/w
r
r/w
r
r/w
r
r
r
xxxx xxxx xxxx xxxx xxxx xxxx x
0
x
0
x
0
0
0
Bit Number
Mnemonic
Description
6
fe
Framing error
Indicates that a framing error was detected.
4
ov
Overrun
Indicates that one or more character have been lost due to overrun.
2
th
Transmitter hold register empty
Indicates that the transmitter hold register is empty.
1
ts
Transmitter shift register empty
Indicates that the transmitter shift register is empty.
0
dr
Data ready
Indicates that new data is available in the receiver holding register.
Bit Number
Mnemonic
Description



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