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AT697F Datasheet(PDF) 119 Page - ATMEL Corporation |
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AT697F Datasheet(HTML) 119 Page - ATMEL Corporation |
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119 / 155 page ![]() AT697F ADVANCE INFORMATION 119 7703C–AERO–6/09 Note: 1. Bits are cleared when written with a 1. Writing a 0 to the register has no effect. 2 tbeer Target byte enable error ‘0’ = disable ‘1’ = enable 1 tper Target parity error ‘0’ = disable ‘1’ = enable 0 syser System error asserted on PCI bus ‘0’ = disable ‘1’ = enable Table 108. PCI Interrupt Pending Register - PCIITP(1) Address = 0x80000168 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w 0x0000 00 0 0 0 0 0 0 0 0 Bit Number Mnemonic Description 7 dmaer DMA end of transfer ‘0’ = not pending ‘1’ = pending 6 imier Initiator error ‘0’ = not pending ‘1’ = pending 5 cmfer PCI core error ‘0’ = not pending ‘1’ = pending 4 imper Initiator Parity error ‘0’ = not pending ‘1’ = pending 3 tier Target error ‘0’ = not pending ‘1’ = pending 2 tbeer Target byte enable error ‘0’ = not pending ‘1’ = pending 1 tper Target parity error ‘0’ = not pending ‘1’ = pending 0 syser System error asserted on PCI bus ‘0’ = not pending ‘1’ = pending Bit Number Mnemonic Description |
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