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AT697F Datasheet(PDF) 115 Page - ATMEL Corporation |
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AT697F Datasheet(HTML) 115 Page - ATMEL Corporation |
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115 / 155 page ![]() Table 98. PCI Retry _trdy - PCIRT Address = 0x80000140 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved retry[7:0] trdy[7:0] r/w r/w 0 0x80 0x80 Bit Number Mnemonic Description 15..8 retry[7:0] Indicates the number of retry the core will performe when configured as master 7..0 trdy[7:0] Indicates the number of PCI clock the processor configured as master will wait for TRDY Table 99. PCI Configuration Write Register - PCICW Address = 0x80000144 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ben[3:0] r/w r/w 0x0000 000 0x0 Bit Number Mnemonic Description 3..0 ben[3:0] Byte enables for writes to the PCI core configuration space ‘0’ = enabled ‘1’ = disabled AT697F ADVANCE INFORMATION 115 7703C–AERO–6/09 Each of the 4 bits is assigned to one 8-bit lane. • bit ben[3] is applied to Byte 3, the most significant byte (MSB) • bit ben[2] is applied to Byte 2 • bit ben[1] is applied to Byte 1 • bit ben[0] is applied to Byte 0, the less significant byte (LSB) Table 100. PCI Initiator Start Address - PCISA Address = 0x80000148 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 start address [31:0] r/w x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Bit Number Mnemonic Description 31..0 start address [31:0] PCI start address for PCI initiator transactions in APB and DMA mode. |
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