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AT697F Datasheet(PDF) 116 Page - ATMEL Corporation

Part # AT697F
Description  Rad-Hard 32 bit SPARC V8 Processor
PDF  155 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT697F Datasheet(HTML) 116 Page - ATMEL Corporation

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Table 101. PCI Initiator Write Register - PCIIW
Address = 0x8000014C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ben[3:0]
r/w
r/w
0x0000 000
0x0
Bit Number
Mnemonic
Description
3..0
ben[3:0]
Byte enables for writes to the PCI core configuration space
‘0’ = enabled
‘1’ = disabled
116
7703C–AERO–6/09
AT697F ADVANCE INFORMATION
Each of the 4 bits is assigned to one 8-bit lane.
•
bit ben[3] is applied to Byte 3, the most significant byte (MSB)
•
bit ben[2] is applied to Byte 2
•
bit ben[1] is applied to Byte 1
•
bit ben[0] is applied to Byte 0, the less significant byte (LSB)
Table 102. PCI DMA configuration Register - PCIDMA
address = 0x80000150
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
com[3:0]
wdcnt[7:0]
r/w
r/w
r/w
0x0000 0
0
0x0
0x00
Bit Number
Mnemonic
Description
12
b2b
Use back2back-mode.
Can be written to 1, if this transaction is to the same target, as the last one.
Note: works only, if the core is enabled for back2back mode.
11..8
com[3:0]
PCI command to be used in DMA mode.
7..0
wdcnt[7:0]
Word count.
Minimum number of words for the burst.
Table 103. PCI Initiator Status Register - PCIIS
address = 0x80000154
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
sys
dmas[3:0]
act
xff
xfe rfe
ss[3:0]
r/w
r
r
r
r
r
r
r
0x0000 0
x
0x0
0
0
1
1
0x0



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