AT697F datasheet(111/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

111

7703C–AERO–6/09

com1

Enable target IO command response

Controls a device's response to I/O Space accesses. A value of 0 disables the device response. A value of 1

allows the device to respond to I/O Space accesses. State after RST* is 0.

Table 90. PCI Device Identification 2 - PCIID2

Address = 0x80000108

class code [23:0]

revision id [7:0]

0x0B4000

0x10

Bit Number

Mnemonic

Description

31..8

class code [23:0]

The Class Code register is read-only and is used to identify the generic function of the device and, in some

cases, a specific register-level programming interface. The register is broken into three byte-size fields. The

upper byte (at offset 0Bh) is a base class code which broadly classifies the type of function the device performs.

The middle byte (at offset 0Ah) is a sub-class code which identifies more specifically the function of the device.

The lower byte (at offset 09h) identifies a specific register-level programming interface (if any) so that device

independent software can interact with the device.

7..0

revision id [7:0]

This register specifies a device specific revision identifier. The value is chosen by the vendor. Zero is an

acceptable value. This field should be viewed as a vendor defined extension to the Device ID.

Table 91. Bist, Header type, Latency, Cache line size Register - PCIBHLC

Address = 0x8000010C

bist[7:0]

header type [7:0]

latency timer [7:0]

cache line size [7:0]

r/w

0x00

Bit Number

Mnemonic

Description

31..24

bist[7:0]

bist7 : Return 1 if device supports BIST. Return 0 if the device is not BIST capable.

bist6 : Write a 1 to invoke BIST. Device resets the bit when BIST is complete. Software should fail the device if

BIST is not complete after 2 seconds.

bist[3..0] : A value of 0 means the device has passed its test. Non-zero values mean the device failed. Device-

specific failure codes can be encoded in the non-zero value.

23..16

header type [7:0]

header 7 : multi-function device

“0” : device is single function

“1” : device is multi-function

header[6..0] : header second part layout

15..8

latency timer [7:0] this field specifies the value for latency timer in PCI bus clock unit

7..0

cache line size

[7:0]

Specifies the cache line size

Bit Number

Mnemonic

Description

AT697F Datasheet(PDF) 111 Page - ATMEL Corporation

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