AT697F datasheet(110/155 Pages) ATMEL

110 / 155 page

110

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

stat8

Master received/asserted PERR

This bit is only implemented by bus masters. It is set when three conditions are met:

1) the bus agent asserted PERR* itself (on a read) or observed PERR* asserted (on a write);

2) the agent setting the bit acted as the bus master for the operation in which the error occurred;

3) the Parity Error Response bit (Command register) is set.

stat7

Target supports fast back2back

This optional read-only bit indicates whether or not the target is capable of accepting fast back-to-back

transactions when the transactions are not to the same agent. This bit can be set to 1 if the device can accept

these transactions and must be set to 0 otherwise.

stat6

User definable features

stat5

66 MHz capabality

This optional read-only bit indicates whether or not this device is capable of running at 66 MHz as defined in

Chapter 7. A value of zero indicates 33 MHz. A value of 1 indicates that the device is 66 MHz capable

stat4

Power management capability.

This optional read-only bit indicates whether or not this device implements the pointer for a New Capabilities

linked list at offset 34h. A value of zero indicates that no New Capabilities linked list is available. A value of one

indicates that the value read at offset 34h is a pointer in Configuration Space to a linked list of new capabilities.

com10

Interrupt command.

This bit disables the device/function from asserting INTx*. A value of 0 enables the assertion of its INTx*

signal. A value of 1 disables the assertion of its INTx* signal. This bit’s state after RST* is 0.

com9

Master can generate fast back2back.

This optional read/write bit controls whether or not a master can do fast back-to-back transactions to different

devices. Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1 means the

master is allowed to generate fast back-to-back transactions to different agents. A value of 0 means fast back-

to-back transactions are only allowed to the same agent. This bit's state after RST* is 0.

com8

Enable SERR driver

-This bit is an enable bit for the SERR* driver. A value of 0 disables the SERR* driver. A value of 1 enables

the SERR* driver. This bit's state after RST* is 0. All devices that have an SERR* pin must implement this bit.

Address parity errors are reported only if this bit and bit 6 are 1.

com7

Address/Data stepping on PCI bus

com6

Enable Parity Check

This bit controls the device's response to parity errors. When the bitis set, the device must take its normal

action when a parity error is detected. When the bit is 0, the device sets its Detected Parity Error status bit (bit

15 in the Status register) when an error is detected, but does not assert PERR* and continues normal

operation. This bit's state after RST* is 0. Devices that check parity must implement this bit. Devices are still

required to generate parity even if parity checking is disabled.

com5

VGA palette snooping

This bit controls how VGA compatible and graphics devices handle accesses to VGA palette registers. When

this bit is 1, palette snooping is enabled (i.e., the device does not respond to palette register writes and snoops

the data). When the bit is 0, the device should treat palette write accesses like all other accesses. VGA

compatible devices should implement this bit.

com4

Enable memory write and invalidate. This is an enable bit for using the Memory Write and Invalidate command.

When this bit is 1, masters may generate the command. When it is 0, Memory Write must be used instead.

State after RST* is 0. This bit must be implemented by master devices that can generate the Memory Write and

Invalidate command.

com3

Enable special cycles

Controls a device's action on Special Cycle operations. A value of 0 causes the device to ignore all Special

Cycle operations. A value of 1 allows the device to monitor Special Cycle operations. State after RST* is 0.

com2

Enable PCI master

Controls a device's ability to act as a master on the PCI bus. A value of 0 disables the device from generating

PCI accesses. A value of 1 allows the device to behave as a bus master. State after RST* is 0.

com1

Enable target memory command response

Controls a device's response to Memory Space accesses. A value of 0 disables the device response. A value of

1 allows the device to respond to Memory Space accesses. State after RST* is 0.

Bit Number

Mnemonic

Description

AT697F Datasheet(PDF) 110 Page - ATMEL Corporation

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