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AT697F Datasheet(PDF) 109 Page - ATMEL Corporation |
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AT697F Datasheet(HTML) 109 Page - ATMEL Corporation |
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109 / 155 page ![]() AT697F ADVANCE INFORMATION 109 7703C–AERO–6/09 PCI Registers Table 88. PCI Device Identification Register 1 - PCIID1 Address = 0x80000100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 device id [15:0] vendor id [15:0] r r 0x1202 0x1438 Bit Number Mnemonic Description 31..16 device id [15:0] This field identifies the particular device. This identifier is allocated by the vendor. 15..0 vendor id [15:0] This field identifies the manufacturer of the device. Valid vendor identifiers are allocated by the PCI SIG to ensure uniqueness. 0FFFFh is an invalid value for Vendor ID. Table 89. PCI Status - Command Register - PCISC Address = 0x80000104 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rr rr rr rr rr r rr r r r r r r r/w r/w r/w r r/w r r/w r r/w r/w r/w 0 0 0 0 0 01 0 1 0 0 0 0 0x0000 0000 0 0 0 0 0 0 0 0 0 0 0 Note: 1. rr = Read and Reset by writing 1 Bit Number Mnemonic Description 31 stat15 Parity error detected. This bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled (as controlled by bit 6 in the Command register). 30 stat14 SERR asserted. This bit must be set whenever the device asserts SERR*. Devices who will never assert SERR* do not need to implement this bit. 29 stat13 Master has terminated master abort. This bit must be set by a master device whenever its transaction except for Special Cycle) is terminated with Master-Abort. All master devices must implement this bit. 28 stat12 Master has terminated target abort This bit must be set by a master device whenever its transaction is terminated with Target-Abort. All master devices must implement this bit. 27 stat11 Target signal target abort. This bit must be set by a target device whenever it terminates a transaction with Target-Abort. Devices that will never signal Target-Abort do not need to implement this bit. 26..25 stat10_9[1:0] Devsel timing. These bits encode the timing of DEVSEL*. Three allowable timings for assertion of DEVSEL* are specified. These are encoded as 00 for fast, 01 for medium, and 10 for slow (11b is reserved). These bits are read-only and must indicate the slowest time that a device asserts DEVSEL* for any bus command except Configuration Read and Configuration Write. |
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