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33902 Datasheet(PDF) 22 Page - Freescale Semiconductor, Inc

Part # 33902
Description  High Speed CAN Interface with Embedded 5.0 V Supply
PDF  31 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33902 Datasheet(HTML) 22 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
22
Freescale Semiconductor
33902
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Distinction Between P_SPI and Traditional Operation.
The distinction between static device control and control
via P_SPI is performed by the duration of the EN and STBY
level. If the EN and STBY levels change before a time of
“tDEV-TR” then the device detects a P_SPI operation. If the EN
and / or STBY levels are stable for a time longer than 15
μs,
then the device state will be changed according to EN / STBY
level and device state diagram.
This means that the device mode change is done after a
delay of typ tDEV-TR and consequently the P_SPI frequency
operation should be faster than (1 / (2 * tDEV-TR).
With tDEV-TR = 8.0 μs, the SPI equivalent frequency should
be greater than 62.5 kHz.
End of P_SPI Message:
At the P_SPI message, the state of EN and STBY pins
should be in line with the device mode expectation:
example:
If the device is in Normal mode and should stay in Normal
mode after the P_SPI command, the EN and STBY pins
should be 1,1 at end of the P_SPI command.
If the device is in Listen Only mode, EN and STBY pins
should be 0,1, in order to set or maintain the device in Listen
Only mode.
Time between 2 P_SPI Message:
A min delay of 15
μs should be observed between two
P_SPI messages.
The delay is measured between the last transition of the
EN/STBY of the 1st message, and the 1st EN/STBY
transition of the next message.
P_SPI Availability:
The P_SPI is operating only in Normal and Listen Only
mode. It is not operating in Standby and Sleep modes.
Table 8 is the mapping of the P_SPI register.
Low power mode definition: Standby, Go To Sleep and
Sleep modes.
Table 8. P_SPI Bit Mapping
D7
D6
D5
D4
D3
D2
D1
D0
MOSI
STAR
T
ADRR
Rb/W
MOSI 4
MOSI 3
MOSI 2
MOSI 1
MOSI 0
MISO
ERR
ACK=ER
Rb
MISO 5
MISO 4
MISO 3
MISO 2
MISO 1
MISO 0
MOSI
STAR
T
0
0 (read)
0
1
0
1
0
1
0
1
0
1
MISO
ERR
ACK=ER
Rb
0
BATFA
IL
X
LxWU WILS CANW
U
Test/
def
VMONF SPIerr
CANF
0
MOSI
STAR
T
0
1 (write)
ERR_EXT
CAN SR1
CAN SR0
CAN WU - pattern
CRANK
MISO
ERR
ACK=ER
Rb
0
0
PASS ID1
PASS ID0
MET ID1
MET ID0
MOSI
STAR
T
1
0
1
0
1
0
1
0
1
0
1
0
1
MISO
ERR
ACK=ER
Rb
Bus
dom
VDD
temp
Rx-PR CAN cur Tx-PD VSO
V
CANF2 VSUV CANF1 VIO low CANF0 VDDlo
w
BATFAIL
Description
VSUP voltage < VSUP low threshold, also called Power On flag
Set
VSUP below VBFTH (3.3 V)
Reset
Entering Normal mode or P_SPI reading (Listen Only)
Action
Avoid entering Go To Sleep. Set
ERR low in Listen Only mode coming from low power modes



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