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33902 Datasheet(PDF) 19 Page - Freescale Semiconductor, Inc

Part # 33902
Description  High Speed CAN Interface with Embedded 5.0 V Supply
PDF  31 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33902 Datasheet(HTML) 19 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
19
33902
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CAN BUS DIAGNOSTIC
The aim is to implement a diagnostic of bus short-circuit to
GND, VBAT, and the internal application circuit board 5.0 V.
Several comparators are implemented on the CANH and
CANL lines. These comparators monitor the bus level in the
recessive and dominant states. The information is then
managed by the logic circuitry to properly determine the
failure and report it.
Figure 14. CAN Bus Simplified Structure Truth Table for Failure Detection
Table 7 indicates the state of the comparators in case of a bus failure, and depending upon the driver state.
Detection Principle
In the recessive state, if one of the two bus lines are
shorted to GND, VDD, or VBAT, the voltage at the other line
follows the shorted line, due to the bus termination
resistance. For example: if CANL is shorted to GND, the
CANL voltage is zero, the CANH voltage measured by the Hg
comparator is also close to zero.
In the recessive state, the failure detection to GND or
VBAT is possible. However, it is not possible with the above
implementation to distinguish which of the CANL or CANH
lines are shorted to GND or VBAT. A complete diagnostic is
possible once the driver is turned on, and in the dominant
state.
Number of Samples for Proper Failure Detection
The failure detector requires at least one cycle of the
recessive and dominant states to properly recognize the bus
failure. The error will be fully detected after 5 cycles of the
recessive-dominant states. As long as the failure detection
circuitry has not detected the same error for 5 recessive-
dominant cycles, the error is not reported.
Bus clamping detection
If the bus is detected to be in dominant for a time longer
than (tDOM), the bus failure flag is set and the ERR is set low
in Normal mode.
Such conditions could occur if the CANH line is shorted to
a high voltage. In this case, current will flow from the high
voltage short-circuit through the bus termination resistors
(60
Ω) and then in the Split terminal (if used), and through the
device CANH and CANL input resistors, which are terminated
to an internal 2.5 V biasing or to GND (Sleep mode).
Depending upon the high voltage short-circuit, the number
of nodes, usage of split terminal, RIN actual resistor, and
node state (sleep or active), the voltage developed across the
bus termination can be sufficient to create a positive
dominant voltage between CANH and CANL. The RXD pin
will be low. This would prevent the start of any CAN
Table 7. Failure Detection Truth Table
Failure description
Driver recessive state
Driver dominant state
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
No failure
1
1
0
1
CANL to GND
0
0
0
1
CANH to GND
0
0
0
0
Lb (threshold VSUP-2.0 V)
Hb (threshold VSUP-2.0 V)
Lb (threshold VSUP-2.0 V)
Hb (threshold VSUP-2.0 V)
No failure
0
0
0
0
CANL to VBAT
1
1
1
1
CANH to VBAT
1
1
0
1
L5 (threshold VDD-0.43 V)
H5 (threshold VDD-0.43 V)
L5 (threshold VDD-0.43 V)
H5 (threshold VDD-0.43 V)
No failure
0
0
0
0
CANL to 5.0 V
1
1
1
1
CANH to 5.0 V
1
1
0
1
Hg
CANH
CANL
Lg
VDD
VRG
VRG
Hb
VRVB
Lb
VRVB
Logic
TX
Diag
VDD (5.0 V)
GND (0.0 V)
Recessive level (2.5 V)
VBAT (12-14 V)
VRVB (VSUP-2.0 V)
VRG (1.75 V)
CANL dominant level (1.4 V)
CANH dominant level (3.6 V)
L5
VR5
H5
VR5
VR5 (VDD-.43 V)



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